-----------------------------------------------------------------------------------
--|
--| Filename:     sg_top_level.vhd
--|
--| Contents:     Entity          :  sg_top
--|               Architecture    :  sg_top__rtl
--|
--| Description:  The program is the top level collection of components for the
--|               signal generator
--|               
--|               
--|
--| Author:       C. Talsma (derived from Xilinx AppNote XAPP154, Sept, 1999)
--|
--| Version:      1.0
--|
--| Revision History:
--|   Date:    
--|   By:    
--|   Change:
--|
--|
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity sg_top is
port(
    BUTTON   : in  std_logic;
	 CLK50M   : in  std_logic;
	 SWCLK    : in  std_logic_vector (3 downto 0);
    SWWAVE   : in  std_logic_vector (1 downto 0);
    DAC_OUT  : out  std_logic;
    CLK25M   : out std_logic;
    CLK12M   : out std_logic;
    CLK6M    : out std_logic;
    CLK3M    : out std_logic;
    CLK1M    : out std_logic;
    CLK780K  : out std_logic;
    CLK390K  : out std_logic;
    CLK195K  : out std_logic;
    CLK97K   : out std_logic;
    CLK48K   : out std_logic;
    CLK24K   : out std_logic;
    CLK12K   : out std_logic;
    CLK6K    : out std_logic;
    CLK3K    : out std_logic;
    CLK1_5K  : out std_logic;
	 RDCLK    : out std_logic
);
end sg_top;

architecture sg_top_rtl of sg_top is

    
component IBUFG
port (
	I : in  std_logic; 
	O : out std_logic
);
end component;

component siggen 
port (
    RESET    : in  std_logic;
    CLK50M   : in  std_logic;
	 SWCLK    : in  std_logic_vector (3 downto 0);
    SWWAVE   : in  std_logic_vector (1 downto 0);
    GEN_OUT  : out std_logic_vector (15 downto 0);
    CLK25M   : out std_logic;
    CLK12M   : out std_logic;
    CLK6M    : out std_logic;
    CLK3M    : out std_logic;
    CLK1M    : out std_logic;
    CLK780K  : out std_logic;
    CLK390K  : out std_logic;
    CLK195K  : out std_logic;
    CLK97K   : out std_logic;
    CLK48K   : out std_logic;
    CLK24K   : out std_logic;
    CLK12K   : out std_logic;
    CLK6K    : out std_logic;
    CLK3K    : out std_logic;
    CLK1_5K  : out std_logic;
	 RDCLK    : out std_logic
);
end component;

component dac
port (
    RESET    : in  std_logic;
    CLOCK    : in  std_logic;
    DAC_IN   : in  std_logic_vector (15 downto 0);
    DAC_OUT  : out std_logic
);
end component;



signal gen_signal : std_logic_vector (15 downto 0);
signal reset      : std_logic;

begin

u1 : IBUFG
port map(
    I => BUTTON,
    O => reset
);

u2 : siggen
port map ( 
    RESET    => RESET,
    CLK50M   => CLK50M,
	 SWCLK    => SWCLK,
    SWWAVE   => SWWAVE,
    GEN_OUT  => gen_signal,
    CLK25M   => CLK25M,
    CLK12M   => CLK12M,
    CLK6M    => CLK6M,
    CLK3M    => CLK3M,
    CLK1M    => CLK1M,
    CLK780K  => CLK780K,
    CLK390K  => CLK390K,
    CLK195K  => CLK195K,
    CLK97K   => CLK97K,
    CLK48K   => CLK48K,
    CLK24K   => CLK24K,
    CLK12K   => CLK12K,
    CLK6K    => CLK6K,
    CLK3K    => CLK3K,
    CLK1_5K  => CLK1_5K,
	 RDCLK    => RDCLK
 );


u3 : dac
port map ( 
    RESET   => reset,
    CLOCK   => CLK50M,
    DAC_IN  => gen_signal,
    DAC_OUT => DAC_OUT
);

  
  
end sg_top_rtl;
